CYWM6934 data transmit receive problem

Sir,
I m using LPC2138 with CYWM6934 for data communication with another radio module (CYWM6934 ) together with Z8F6423 at the other end.
In transmit code the steps followed are-
1-nPD & nRESET are first LOW then with a delay of 5 mS HIGH .
2-Radio registers initialized with values REG_CLOCK_MANUAL=0x41,REG_CLOC K_ENABLE=0x41,REG_CHANNEL=0x02 ,REG_DATA_RATE=0x06,REG_SERDES _CTL=0x0B,REG_ANALOG_CTL=0x44, REG_PWR_CTL=0x80,REG_PA=0x07,R EG_XTAL_ADJ=0x40,REG_VCO_CAL=0 xC0,REG_TX_VALID=0xFF,REG_CONF IG=0x01.
3-In the interrupt service routine of IRQ from CYWM6934 ,only a irqflag is made high.
3-Then in while loop LPC2138 waits continuously for push button interrupt.And when it comes Empty Interrupt (REG_TX_INT_EN=0x01) & Tx(REG_CONTROL=0x52) are enabled.
4-Then REG_TX_INT_STAT is read .it is showing value 0x1.
5-After that REG_TX_DATA is written with databyte. Then again on reading the REG_TX_INT_STAT it shows 0xb.
Then it waits for IRQ to assert using "while(irqflag != TRUE) ;"
6-After that another byte is written in REG_TX_DATA.
7-Then Tx Done Interrupt is enabled in REG_TX_INT_EN(0x02).
8-Then it again waits for IRQ to assert using "while(irqflag != TRUE) ;"
9-After tht transmission is Disabled by REG_CONTROL=0x12.

In receive code the steps followed are-
1.PD and RST pulled low
2.PD and RST pulled high after delay
3. initialize radio registers for 32chips ,double datarate with default threshold values.VCO cal for +/-5
4.receive full and EOFA interrupt enable
5.receive enable
6.wait for receive interrupt in while loop.
Not receiving the receive interrupt.

Will u plz tell me that the problem is either in transmit code or in receive code.
Thanks .

To transmit:

BYTE RadioTransmit(BYTE len, BYTE *txbuf)
{
BYTE i;
radio_status[0]= SpiRead((SPI_FRZ | 0x0E)); //REG_TX_INT_STAT - clear transmit status
SpiWrite((SPI_FRZ | 0x0D), 0x01); //REG_TX_INT_EN - enable empty flag on IRQ pin
SpiWrite((SPI_FRZ | 0x03), 0x50); //REG_CONTROL - enable tx
DelayMicroSec(SYNTH_SETTLE); // wait for synth to settle
DelayMicroSec(PREAMBLE); // delay in loading txbuf to send extra preamble symbol
for(i=0;i<len;i++){
SpiWrite((SPI_FRZ | 0x0F), txbuf[i]); //REG_TX_DATA - send data
while(!IRQ); // wait 'til REG_TX_DATA empty
}
SpiWrite((SPI_FRZ | 0x0D), 0x02); //REG_TX_INT_EN - enable done flag on IRQ pin
while(!IRQ); // wait 'til REG_TX_DATA done
SpiWrite((SPI_FRZ | 0x03), 0x00); //REG_CONTROL - return to idle
radio_status[0]= SpiRead((SPI_FRZ | 0x0E)); //REG_TX_INT_STAT - clear transmit status
return(radio_status[0]);
}

To receive:

BYTE RadioReceive(BYTE *rxbuf)
{
BYTE len = 0;
radio_status[2]= SpiRead((SPI_FRZ | 0x08)); //REG_RX_INT_STAT - clear receive status
SpiWrite((SPI_FRZ | 0x07), 0x03); //REG_RX_INT_EN - enable EOFA and FULLA flags on IRQ pin
SpiWrite((SPI_FRZ | 0x03), 0x90); //REG_CONTROL - enable rx
DelayMicroSec(SYNTH_SETTLE); // wait for synth to settle
DelayMicroSec(RECEIVER_READY); // wait for receiver afe ready
while(1){
while(!IRQ); // wait 'til either EOFA or FULLA receive flag fires
radio_status[2]= SpiRead((SPI_FRZ | 0x08)); //REG_RX_INT_STAT - check receive status
if(radio_status[2]&0x01){/ /store REG_RX_DATA_A and REG_RX_VALID_A in user's rxbuf
SpiFileRead((SPI_INC | 0x09), 2, &rxbuf[len]);
if(rxbuf[len+1] > 3) len += 2;
}
if(radio_status[2]&0x02 && len) break;
if(len > sizeof(radio_rxbuf)){
len = sizeof(radio_rxbuf);
break;
}
}//~75usec of "idle" time between bytes when using 64kbps
SpiWrite((SPI_FRZ | 0x03), 0x00); //REG_CONTROL - return to idle
radio_status[5]= SpiRead((SPI_FRZ | 0x22)); // store REG_RSSI
return(len);
}